ST Micro LoRa SoC

3rd Generation LoRa via New SoC from STMicro

Just in time for CES, STMicro has released a new SoC (System on Chip) that contains an STM32L4 and a LoRa transceiver.  Here’s a link to the product page.  The long-story-short is that Haystack will be adopting this SoC in our products in 1st half 2020, and it will improve our performance.

The STM32WLE chips are noteworthy for being true SoCs.  They are not multi-chip packages, so the cost should be attractive to anyone building LoRa endpoints.  It’s basically just a SX1262 and STM32L4 bolted onto the same die, but a careful reading of the product manual reveals there are a few novel features, at least three of them described below:

1. Flexible Power Routing Improves System Efficiency

Lots of power routing features to get optimum energy efficiency from the LoRa transceiver without extra ICs required.  In previous Haystack designs, in order to get best efficiency across the range of transmission power, we needed to add an extra power supply, load switch, and in some cases an SP3T RF switch (LoRa can get quite power-hungry if you’re not careful).  We can get rid of most of these extra parts, now, and replace them with firmware on the STM32WLE.  Efficiency will improve, size can be smaller, and cost can be less.

2. Multi-PHY Support

Radio PHYs that appear to support all SigFox modes and even, it seems, Sony ElTres modes.  Obviously, it also supports LoRaWANmeaning this SoC can support all the major LPWANs available in 2020.

3. Door is Open for Unrestricted Usage of Advanced Error Correction

It is now an official, supported feature to disable the Hamming coding.  In all previous LoRa literature, there’s no indication about this being possible or supported.  Now it is.  The consequence is positive: users of advanced error correction, such as Haystack’s XR2, immediately get more than 20% efficiency improvement by disabling the useless Hamming coding (the gain beyond 20% comes from the direct sequencing of the LoRa PHY gray code onto the XR2 code, without any gaps from parity bits).

This 3rd point is especially important to us at Haystack, and it’s what we believe makes this chip a “3rd generation” LoRa rather than a 2nd or 2.5G LoRa.  It gives us the ability to innovate and improve performance in a way that deserves a whole generation, not a half (more to come on this, soon).

And, Something Odd…

In STMicro’s Reference manual, the sensitivity figures (the minimum SNR figures) given at different spreading factors are different than those listed in the Semtech data sheets.  These are particularly notable at higher spreading factors, as you’ll loose 1 dB at SF12.  It’s uncertain if these figures are due to application of better testing than Semtech had done previously (their lab benchmarks are suspicious and much more optimistic than our own testing), or simply higher noise levels in the integrated package.  In either case, Haystack’s XR2 error correction coding, combined with the removal of the parasitic Hamming coding, will easily overcome any sensitivity deficit.

Other Points of Interest

Other novel features, or at least one we’ve never seen before, are inclusion of hardware semaphores in the STM32WLE core and a Public-Key Cryptography accelerator.  OpenTag (our FW BIOS) will definitely make use of these.  The hardware semaphores will make it much easier to integrate a guest RTOS (e.g. Zephyr) above the OpenTag BIOS.  This is something we’ve wanted to do for a long time, and finally, now, there are the features available (and enough SRAM) to make it practical.  The Public Key Accelerator will do a lot to improve secure key exchanges at the edge of an IoT network — again, something we’ve been waiting to do for a long time, and a feature that will make DASH7 over LoRa far more compelling to security-conscious users of LoRaWAN.

Haystack will be migrating to the STM32WLE platform in the first half of 2020, for endpoints and also for compact one and two channel gateways.